DRAM timings
Aug. 11th, 2006 08:36 pm![[personal profile]](https://www.dreamwidth.org/img/silk/identity/user.png){kind=small}
lprovenLet me see if I have this straight...
A friend asked if DRAM had gotten much faster since the days of 70ns and 60ns memory. I had to do quite a lot of digging to answer him...
Working out timings for SDRAM was relatively simple. PC100 SDRAM runs at 100MHz, so the cycle time was 10ns. (1ns => 1GHz.) PC133 SDRAM ran at about 7.5ns.
Then came DDR, which sends data on both the rising and falling edge of the signal. That doubles the speed: 100MHz DDR sends data at 200MHz. The fastest DDR is DDR400, running at 200MHz, so though each clock cycle is 5ns, the data is returned in 2.5ns.
DDR2 is not quad-pumped; it's just a refinement of DDR for faster operation. It will be followed by DDR3. The next big step up would be QDR, quad-pumped, but that's still in the labs and isn't working well yet.
The fastest commonly-available RAM around today is DDR2-800, running at a clock rate of 200MHz but which can handle 2 I/O cycles per clock. This is used to make PC2-6400 DIMMs, offering 6.4Gb/s bandwidth - that's 64 bits of data twice every clock cycle.
With DDR and especially DDR2, though, it gets complicated. They're variants of SDRAM, which means they only hit full speed doing long sequential reads from the same row of memory cells. Random access speed is a lot lower; that's why vendors cite latency speeds. So different accesses will run at different speeds, which I guess is why we no longer get "60ns" or something stated: it's too variable to do that now.
I'm not confident about this working, so I'll show it for possible correction...
The best speed from a PC2-6400 DIMM would be:
64GB/s, i.e.,
64 x 1,073,741,824 bytes = 68,719,476,736 bytes per second
That's 1.4551915228366851806640625 × 10-11 seconds per byte. 1ns is 10-9 of a second, so this (rounded) is equivalent to 0.01456 of a nanosecond, or around 14 picoseconds (10-12) of a second.
Crucial lists the latencies of their own PC2-8000 DDR2 SDRAM as 5-5-5-12. The 1st value is CAS (Column Address Strobe) latency, the 2nd RAS (Row Address Strobe) to CAS delay, the 3rd RAS precharge, the last DRAM precharge.
(Compare this to 3-4-4-8 for their DDR; this is why AMD dragged their feet moving from DDR to DDR2 and why AM2 CPUs are actually a little slower. When you don't get a nice direct successive read, you get punished by the higher latencies.)
AIUI, these latencies imply a delay of around 5 cycles for changing address and an initial warm-up period of 12 cycles.
But overall, yes, it's sped up a lot since the days of 60ns FP-DRAM. This stuff is responding in a pretty reasonable timeframe for 3-4GHz processors, really!
(This grew in the telling as I tried to get it straight in my head. Corrections welcome!)
And in other news, my first book from BookMooch has arrived! Yay! Next I have to send one to America, though. That's going to cost me. :¬( However, I've already requested another one and I have about 3 pending. So come on, join & mooch some books from me so that I can get enough points to mooch more myself! :¬)
A friend asked if DRAM had gotten much faster since the days of 70ns and 60ns memory. I had to do quite a lot of digging to answer him...
Working out timings for SDRAM was relatively simple. PC100 SDRAM runs at 100MHz, so the cycle time was 10ns. (1ns => 1GHz.) PC133 SDRAM ran at about 7.5ns.
Then came DDR, which sends data on both the rising and falling edge of the signal. That doubles the speed: 100MHz DDR sends data at 200MHz. The fastest DDR is DDR400, running at 200MHz, so though each clock cycle is 5ns, the data is returned in 2.5ns.
DDR2 is not quad-pumped; it's just a refinement of DDR for faster operation. It will be followed by DDR3. The next big step up would be QDR, quad-pumped, but that's still in the labs and isn't working well yet.
The fastest commonly-available RAM around today is DDR2-800, running at a clock rate of 200MHz but which can handle 2 I/O cycles per clock. This is used to make PC2-6400 DIMMs, offering 6.4Gb/s bandwidth - that's 64 bits of data twice every clock cycle.
With DDR and especially DDR2, though, it gets complicated. They're variants of SDRAM, which means they only hit full speed doing long sequential reads from the same row of memory cells. Random access speed is a lot lower; that's why vendors cite latency speeds. So different accesses will run at different speeds, which I guess is why we no longer get "60ns" or something stated: it's too variable to do that now.
I'm not confident about this working, so I'll show it for possible correction...
The best speed from a PC2-6400 DIMM would be:
64GB/s, i.e.,
64 x 1,073,741,824 bytes = 68,719,476,736 bytes per second
That's 1.4551915228366851806640625 × 10-11 seconds per byte. 1ns is 10-9 of a second, so this (rounded) is equivalent to 0.01456 of a nanosecond, or around 14 picoseconds (10-12) of a second.
Crucial lists the latencies of their own PC2-8000 DDR2 SDRAM as 5-5-5-12. The 1st value is CAS (Column Address Strobe) latency, the 2nd RAS (Row Address Strobe) to CAS delay, the 3rd RAS precharge, the last DRAM precharge.
(Compare this to 3-4-4-8 for their DDR; this is why AMD dragged their feet moving from DDR to DDR2 and why AM2 CPUs are actually a little slower. When you don't get a nice direct successive read, you get punished by the higher latencies.)
AIUI, these latencies imply a delay of around 5 cycles for changing address and an initial warm-up period of 12 cycles.
But overall, yes, it's sped up a lot since the days of 60ns FP-DRAM. This stuff is responding in a pretty reasonable timeframe for 3-4GHz processors, really!
(This grew in the telling as I tried to get it straight in my head. Corrections welcome!)
And in other news, my first book from BookMooch has arrived! Yay! Next I have to send one to America, though. That's going to cost me. :¬( However, I've already requested another one and I have about 3 pending. So come on, join & mooch some books from me so that I can get enough points to mooch more myself! :¬)
